Many electronic systems include circuits, such as switching power converters or transformers that interface with a dimmer. The interfacing circuits deliver power to a load in accordance with the dimming level set by the dimmer. For example, in a lighting system, dimmers provide an input signal to the lighting system. The input signal represents a dimming level that causes the lighting system to adjust power delivered to a lamp, and, thus, depending on the dimming level, increase or decrease the brightness of the lamp. Many different types of dimmers exist. In general, dimmers generate an output signal in which a portion of an alternating current (“AC”) input signal is removed or zeroed out. For example, some analog-based dimmers utilize a triode for alternating current (“triac”) device to modulate a phase angle of each cycle of an alternating current supply voltage. This modulation of the phase angle of the supply voltage is also commonly referred to as “phase cutting” the supply voltage. Phase cutting the supply voltage reduces the average power supplied to a load, such as a lighting system, and thereby controls the energy provided to the load.
A particular type of a triac-based, phase-cutting dimmer is known as a leading-edge dimmer. A leading-edge dimmer phase cuts from the beginning of an AC cycle, such that during the phase-cut angle, the dimmer is “off” and supplies no output voltage to its load, and then turns “on” after the phase-cut angle and passes phase cut input signal to its load. To ensure proper operation, the load must provide to the leading-edge dimmer a load current sufficient to maintain an inrush current above a current necessary for opening the triac. Due to the sudden increase in voltage provided by the dimmer and the presence of capacitors in the dimmer, the current that must be provided is typically substantially higher than the steady state current necessary for triac conduction. Additionally, in steady state operation, the load must provide to the dimmer a load current to remain above another threshold known as a “hold current” needed to prevent premature disconnection of the triac.
FIG. 1 depicts a lighting system 100 that includes a triac-based leading-edge dimmer 102 and a lamp 142. FIG. 2 depicts example voltage and current graphs associated with lighting system 100. Referring to FIGS. 1 and 2, lighting system 100 receives an AC supply voltage VSUPPLY from voltage supply 104. The supply voltage VSUPPLY indicated by voltage waveform 200 may be, for example, a nominally 60 Hz/110 V line voltage in the United States of America or a nominally 50 Hz/220 V line voltage in Europe. Triac 106 acts as a voltage-driven switch, and a gate terminal 108 of triac 106 controls current flow between the first terminal 110 and the second terminal 112. A gate voltage VG on the gate terminal 108 above a firing threshold voltage value VF will cause triac 106 to turn ON, in turn causing a short of capacitor 121 and allowing current to flow through triac 106 and dimmer 102 to generate an output current iDIM.
Assuming a resistive load for lamp 142, the dimmer output voltage VΦ—DIM, indicated by voltage waveform 206, may be zero volts from the beginning of each of half cycles 202 and 204 at respective times t0 and t2 until the gate voltage VG reaches the firing threshold voltage value VF. Dimmer output voltage VΦ—DIM represents the output voltage of dimmer 102. During time period TOFF, the dimmer 102 chops or cuts the supply voltage VSUPPLY so that the dimmer output voltage VΦ—DIM remains at zero volts during time period tOFF. At time t1, the gate voltage VG reaches the firing threshold value VF, and triac 106 begins conducting. Once triac 106 turns ON, the dimmer voltage VΦ—DIM tracks the supply voltage VSUPPLY during time period tON.
Once triac 106 turns ON, the current iDIM drawn from triac 106 must exceed an attach current iATT in order to sustain the inrush current through triac 106 above a threshold current necessary for opening triac 106. In addition, once triac 106 turns ON, triac 106 continues to conduct current iDIM regardless of the value of the gate voltage VG as long as the current iDIM remains above a holding current value iHC. The attach current value iATT and the holding current value iHC are a function of the physical characteristics of triac 106. Once the current iDIM drops below the holding current value iHC, i.e. iDIM<iHC, triac 106 turns OFF (i.e., stops conducting), until the gate voltage VG again reaches the firing threshold value VF. In many traditional applications, the holding current value iHC is generally low enough so that, ideally, the current iDIM drops below the holding current value iHC when the supply voltage VSUPPLY is approximately zero volts near the end of the half cycle 202 at time t2.
The variable resistor 114 in series with the parallel connected resistor 116 and capacitor 118 form a timing circuit 115 to control the time t1 at which the gate voltage VG reaches the firing threshold value VF. Increasing the resistance of variable resistor 114 increases the time TOFF, and decreasing the resistance of variable resistor 114 decreases the time TOFF. The resistance value of the variable resistor 114 effectively sets a dimming value for lamp 142. Diac 119 provides current flow into the gate terminal 108 of triac 106. The dimmer 102 also includes an inductor choke 120 to smooth the dimmer output voltage VΦ—DIM. Triac-based dimmer 102 also includes a capacitor 121 connected across triac 106 and inductor choke 120 to reduce electro-magnetic interference.
Ideally, modulating the phase angle of the dimmer output voltage VΦ—DIM effectively turns the lamp 142 OFF during time period TOFF and ON during time period TON for each half cycle of the supply voltage VSUPPLY. Thus, ideally, the dimmer 102 effectively controls the average energy supplied to lamp 142 in accordance with the dimmer output voltage VΦ—DIM.
Another particular type of phase-cutting dimmer is known as a trailing-edge dimmer. A trailing-edge dimmer phase cuts from the end of an AC cycle, such that during the phase-cut angle, the dimmer is “off” and supplies no output voltage to its load, but is “on” before the phase-cut angle and in an ideal case passes a waveform proportional to its input voltage to its load.
FIG. 3 depicts a lighting system 300 that includes a trailing-edge, phase-cut dimmer 302 and a lamp 342. FIG. 4 depicts example voltage and current graphs associated with lighting system 300. Referring to FIGS. 3 and 4, lighting system 300 receives an AC supply voltage VSUPPLY from voltage supply 304. The supply voltage VSUPPLY, indicated by voltage waveform 400, is, for example, a nominally 60 Hz/110 V line voltage in the United States of America or a nominally 50 Hz/220 V line voltage in Europe. Trailing-edge dimmer 302 phase cuts trailing edges, such as trailing edges 402 and 404, of each half cycle of supply voltage VSUPPLY. Since each half cycle of supply voltage VSUPPLY is 180 degrees of the supply voltage VSUPPLY, the trailing-edge dimmer 302 phase cuts the supply voltage VSUPPLY at an angle greater than 0 degrees and less than 180 degrees. The phase cut, input voltage VΦ—DIM to lamp 342 represents a dimming level that causes the lighting system 300 to adjust power delivered to lamp 342, and, thus, depending on the dimming level, increase or decrease the brightness of lamp 342.
Dimmer 302 includes a timer controller 310 that generates dimmer control signal DCS to control a duty cycle of switch 312. The duty cycle of switch 312 is a pulse width (e.g., times t1-t0) divided by a period of the dimmer control signal (e.g., times t3-t0) for each cycle of the dimmer control signal DCS. Timer controller 310 converts a desired dimming level into the duty cycle for switch 312. The duty cycle of the dimmer control signal DCS is decreased for lower dimming levels (i.e., higher brightness for lamp 342) and increased for higher dimming levels. During a pulse (e.g., pulse 406 and pulse 408) of the dimmer control signal DCS, switch 312 conducts (i.e., is “on”), and dimmer 302 enters a low resistance state. In the low resistance state of dimmer 302, the resistance of switch 312 is, for example, less than or equal to 10 ohms. During the low resistance state of switch 312, the phase cut, input voltage VΦ—DIM tracks the input supply voltage VSUPPLY and dimmer 302 transfers a dimmer current iDIM to lamp 342.
When timer controller 310 causes the pulse 406 of dimmer control signal DCS to end, dimmer control signal DCS turns switch 312 off, which causes dimmer 302 to enter a high resistance state (i.e., turns off). In the high resistance state of dimmer 302, the resistance of switch 312 is, for example, greater than 1 kiloohm. Dimmer 302 includes a capacitor 314, which charges to the supply voltage VSUPPLY during each pulse of the dimmer control signal DCS. In both the high and low resistance states of dimmer 302, the capacitor 314 remains connected across switch 312. When switch 312 is off and dimmer 302 enters the high resistance state, the voltage VC across capacitor 314 increases (e.g., between times t1 and t2 and between times t4 and t5). The rate of increase is a function of the amount of capacitance C of capacitor 314 and the input impedance of lamp 342. If effective input resistance of lamp 342 is low enough, it permits a high enough value of the dimmer current iDIM to allow the phase cut, input voltage VΦ—DIM to decay to a zero crossing (e.g., at times t2 and t5) before the next pulse of the dimmer control signal DCS.
In some lighting applications, a dimmer may not be directly coupled to a lamp. For example, in applications in which a lamp comprises a low-power lamp (e.g., halogen or light-emitting diode (LED) lamp), a switching power converter may be interfaced between the dimmer and the lamp to convert the AC input voltage to a direct current (DC) voltage to be delivered to the lamp. FIG. 5 depicts a lighting system 500 that includes a lamp assembly 542 with a bridge rectifier 534 and a power converter 536 for converting an AC voltage input to a DC voltage for delivery to a low-power lamp comprising LEDs 532, as is known in the art. As shown in FIG. 5, lighting system 500 may include a voltage supply 504, a dimmer 502, and a lamp assembly 542. Voltage supply 504 may generate a supply voltage VSUPPLY that is, for example, a nominally 60 Hz/110 V line voltage in the United States of America or a nominally 50 Hz/220 V line voltage in Europe.
Dimmer 502 may comprise any system, device, or apparatus for generating a dimming signal to other elements of lighting system 500, the dimming signal representing a dimming level that causes lighting system 500 to adjust power delivered to a lamp, and, thus, depending on the dimming level, increase or decrease the brightness of LEDs 532. Thus, dimmer 502 may include a leading-edge dimmer similar to that depicted in FIG. 1, a trailing-edge dimmer similar to that depicted in FIG. 3, or any other suitable dimmer.
Lamp assembly 542 may comprise any system, device, or apparatus for converting electrical energy (e.g., delivered by dimmer 502) into photonic energy (e.g., at LEDs 532). For example, lamp assembly 542 may comprise a multifaceted reflector form factor (e.g., an MR16 form factor) with a lamp comprising LEDs 532. As shown in FIG. 5, lamp assembly 542 may include a bridge rectifier 534, a power converter 536, and a switch state controller 512.
Bridge rectifier 534 may comprise any suitable electrical or electronic device as is known in the art for converting the whole of alternating current voltage signal VΦ—DIM into a rectified voltage signal vREC having only one polarity.
Power converter 536 may comprise any system, device, or apparatus configured to convert an input voltage (e.g., vREC) to a different output voltage (e.g., vOUT) wherein the conversion is based on a control signal (e.g., a pulse-width modulated control signal communicated from switch state controller 512). Accordingly, power converter 536 may comprise a boost converter, a buck converter, a boost-buck converter, or other suitable power converter.
LEDs 532 may comprise one or more light-emitting diodes configured to emit photonic energy in an amount based on the voltage vOUT across the LEDs 532.
Switch-state controller 512 may comprise any system, device, or apparatus configured to determine one or more characteristics of voltage vREC present at the input of power converter 536 and control an amount of current iREC drawn by power converter 536 based on such one or more characteristics of voltage vREC.
In some embodiments, power converter 536 may comprise a switching power converter, such as a buck converter 536A, as shown in FIG. 6. As shown in FIG. 6, a buck-type power converter 536A may comprise a switch 608 that may operate in response to a control signal CS to regulate the transfer of energy from the rectified, time-varying input voltage VREC, through inductor 610 to capacitor 606. Power converter 536A may also include a diode 611 that prevents reverse current flow from capacitor 606 into inductor 610. Energy transferred through inductor 610 may be stored by capacitor 606. Capacitor 606 may have sufficient capacitance to maintain an approximately constant voltage VOUT (e.g., lesser than the peak of input voltage VREC) while providing current to LEDs 532.
In operation, inductor current iL may vary over time, with a peak input current proportionate to the “on-time” of switch 608 and with the energy transferred to capacitor 606 proportionate to the “on-time” squared. As shown in FIG. 6, in some implementations switch 608 may comprise n-channel field effect transistor (FET), and control signal CS is a pulse-width modulated (PWM) control signal that causes switch 608 to conduct when control signal CS is high. Thus, in such implementations, the “on-time” of switch 608 may be determined by the pulse width of control signal CS, and the energy transferred from VREC to capacitor 606 may be proportionate to a square of the pulse width of control signal CS.
Control signal CS may be generated by switch state controller 512, with a goal of causing switching power converter 536A to transfer a desired amount of energy to capacitor 606, and thus, to LEDs 532. The desired amount of energy may depend upon the voltage and current requirements of LEDs 532. To provide power factor correction close to one, switch state controller 512 may generally seek to control input current iREC so that input current iREC tracks input voltage VREC while holding capacitor voltage VOUT constant. Accordingly, input current iREC and peak inductor current iL may each be proportional to the conduction period of dimmer 502 (e.g., the period of time in which dimmer 502 is on and conducts current).
In implementations in which switch 608 is implemented with a FET, one known problem is that the inherent capacitance of the FET undesirably resonates with inductor 610 after input current in inductor 610 is demagnetized. A known technique to minimize such resonance and to reduce the attendant switching losses is sometimes referred to as “valley switching” in which control signal CS is controlled to turn on switch 608 when the drain-to-source voltage VDS of switch 608 reaches its minimum value.
Referring now to FIG. 7, there is depicted a timing diagram illustrating the concept of valley switching, as is known in the art. In the absence of valley switching, switch state controller 512 may operate so as to maintain a target switching period TT for a particular dimmer control setting. The period TT may be equal to the sum of interval T1, T2, and T3, wherein T1 is an interval of time in which switch 608 is activated and conducts current, T2 is an interval of the time in which switch 608 is deactivated and current iL flows while inductor 610 is demagnetized, and T3 is an interval of time, which may be referred to as a valley interval, in which no current iL flows. However, when implementing valley switching, a valley of drain-to-source voltage VDS may occur before or after the end of target switching period TT. Accordingly, to implement valley switching, switch state controller 512 may assert control signal CS to activate switch 608 before or after the end of target switching period TT, thus modifying the desired switching period by an error TTerr, thus reducing or extending the switching period to obtain an actual switching period TT′. Accordingly, conventional valley-switching techniques lead to reduction or addition in the average current supplied to LEDs 532 from an intended amount. Thus, maintaining constant voltage regulation for a load (e.g., LEDs 532) while performing valley switching is a challenge if switching periods may become quantized to specific valleys. Another challenge is to maintain valley switching throughout an entire phase angle range of a dimmer while maintaining desired output regulation.